A brief description will be given first, with reference to FIG. 1, of a typical prior art active matrix type liquid crystal display cell which has a capacitive storage effect. FIG. 1 shows a liquid crystal display panel 10 in which display pixels 12 are arranged in the form of a matrix (with m rows and n columns) and their display electrodes 12a are connected to drains of TFTs (Thin Film Transistors) 13, respectively. The TFTs 13 have their sources and gates connected to those of perpendicularly intersecting source buses 14.sub.l to 14.sub.n and gate buses 15 which correspond to them, respectively. The display pixels 12 each include a counter electrode (also referred to as a common electrode) 12b disposed opposite the display electrode 12a.
A source bus drive circuit 16 is provided for driving the source buses 14.sub.l through 14.sub.n. From a main body (not shown) of the liquid crystal display device the source bus drive circuit is supplied with a pixel clock PCK, a horizontal synchronizing signal Hs and a control signal M for converting the power supply voltage into an AC form, such as shown in FIG. 2, and pixel data (a binary code representing logic "1" or "0") D which is applied in the horizontal direction in synchronism with the pixel clock PCK, though not shown. In the source bus drive circuit 16 the pixel data D of one row are sequentially loaded into a shift register 16a in synchronism with the pixel clock PCK, and in correspondence to the pixel data D, signals S.sub.l to S.sub.n to be displayed on the pixels of one row of the liquid crystal display panel 10 are ,simultaneously provided on the source buses 14.sub.l and 14.sub.n upon each occurrence of the horizontal synchronizing signal Hs. The signals S.sub.l to S.sub.n are also called source bus drive signals, and they have voltages E.sub.1 and E.sub.2 (in the case of a field M=1) or E.sub.2 and E.sub.3 (in the case of a field M=0) depending upon the logic "1" and "0" of the pixel data D, as shown in FIG. 2D in which one signal S.sub.j is exemplified. Here, E.sub.2 =(E.sub.1 +E.sub.3)/2. The source bus drive circuit 16 operates on the DC voltages E.sub.1, E.sub.2 and E.sub.3 and a common potential EG (zero volt) from the main body of the liquid crystal display device.
The liquid crystal display panel 10 is also supplied with the common potential EG from the main body of the display device and the counter electrodes of the respective pixels are each supplied with a voltage corresponding to the voltage E.sub.2. The common potential EG (zero volt) and the voltages E.sub.1, E.sub.2 and E.sub.3 are selected such that E.sub.1 &gt;EG&gt;E.sub.2 &gt;E.sub.3, for instance.
A gate bus drive circuit 17 drives the gate buses 15.sub.1 to 15.sub.m high-level one after another upon each occurrence of the horizontal synchronizing signal Hs, thereby turning ON the TFTs of one row from the first to the mth row in a sequential order. As a result of this, the source bus drive signals S.sub.l to S.sub.n are applied to the corresponding pixels, respectively. The gate bus drive circuit is made up principally of an m-stage shift register 18 and a gate bus driver 19. A vertical synchronizing signal Vs (FIG. 2E) is applied, as a start signal, to a data terminal D of the first-stage shift register, and the horizontal synchronizing signal Hs is applied to a clock terminal CK of each stage. Pulses, which result from sequential delaying of the start signal for the horizontal synchronizing signal period, are provided from output terminals Q of the respective stages to the gate bus driver 19. In the gate bus driver 19 the input pulses are converted in level, providing on the gate buses 15.sub.l to 15.sub.m gate bus drive signals G.sub.l to G.sub.m (FIG. 2F) each of which has a voltage level V.sub.1 or V.sub.3 depending on whether the input pulse from the corresponding stage is high- or low-level. From the main body of the device the power supply voltages V.sub.1 and V.sub.2 are supplied to the shift register 18 and the gate bus driver 19 and the power supply voltage V.sub.3 is supplied to the gate bus driver 19. These voltages are selected such that V.sub.1 &gt;V.sub.2 &gt;V.sub.3, and in many cases, V.sub.1 -V.sub.2 =5 volts.
To clear a display at a desired time, pixel data for one field (m rows) which have logic "0" for erasing displays of respective pixels are provided from the main body of the device, and upon each occurrence of the horizontal synchronizing signal Hs, voltage E.sub.2 signals for m rows are simultaneously applied from the source bus drive circuit 16 to the source buses 14.sub.l through 14.sub.n and the gate buses 15.sub.l through 15.sub.m are sequentially driven high-level by the gate bus driver 17, whereby the display of one field is cleared. That is, clearing of one field display needs a time mT.sub.H (where T.sub.H is the cycle of the horizontal synchronizing signal) at the shortest. This is not preferable because, for example, when the liquid crystal display panel 10 is used with a computer, the higher the display-clearing frequency, the longer the time for which the computer is occupied.
To stop the display device from the display operation, it is customary to turn OFF the power supply switch of the display device main body without involving any particular display clearing operation mentioned above. Upon turning OFF the switch, various signals provided to the liquid crystal display panel disappear and various power supply voltages also drop to the common potential (the ground potential) within a short time. The output G.sub.i of the gate bus driver also disappears and drops to the common potential. Consequently, all the TFTs 13 of the liquid crystal display panel 10 are turned OFF, and charges stored in pixel capacitances remain undischarged for a relatively long period of time, because their external discharge paths are cut off. This allows residual images to remain on the display screen, impairing the display quality. Furthermore, to leave the pixels stored with charges as mentioned above means that DC voltage remains unremoved from the liquid crystal, shortening its life and lowering its reliability.
An object of the present invention is to provide a liquid crystal display erasing method which permits clearing of a display on a liquid crystal display panel in a markedly shorter time than in the past.
Another object of the present invention is to provide a liquid crystal display erasing circuit which permits clearing of a residual image in a short time upon turning OFF the power supply of a display device and prevents shortening of liquid crystal life and lowering of its reliability.